IP Verification Expert(PCIE)

PCIe Protocol IP Verification Expert – Consulting & Turnkey Projects

Location: San Francisco, CA

Experience: 5–10+ Years

Job Type: Consulting / Turnkey Projects

Job Overview

We are seeking a seasoned PCIe Protocol IP Verification Expert with strong experience in ASIC/SOC/IP verification for AI, HPC, and high-performance data center environments. The ideal candidate will have deep expertise in PCIe protocol verification, IP integration, interoperability, and pre-silicon validation.

The role will focus on integrating third-party PCIe IPs with PCIe Gen6 controller/PHY solutions and validating interoperability across multiple PHY and IP vendors. The candidate will work on complex system-level environments involving the latest PCIe protocol interfaces, switches, and scalable architectures for scale-up and scale-out data centers.

Key Responsibilities


- Perform PCIe IP and SOC-level verification for Gen1 through Gen6/Gen7 environments.
- Integrate and validate third-party PCIe IPs from multiple vendors with PCIe controllers and PHYs.
- Develop and execute comprehensive pre-silicon verification and regression strategies.
- Build and configure subsystem-level environments containing PCIe DUTs, PHYs, Root Complexes, Endpoint Devices, clocks, resets, and required glue logic.
- Develop, modify, and enhance UVM-based verification environments and C/C++ testbenches.
- Debug complex PCIe link-up, enumeration, interoperability, and device bring-up scenarios.
- Analyze and debug LTSSM state-machine behavior and PCIe link training failures.
- Validate PCIe configuration and interoperability across different PCIe generations and device combinations.
- Troubleshoot issues related to PCIe link initialization, enumeration, configuration space, device IDs, and driver/device interaction.
- Work closely with RTL, firmware, software, PHY, and system integration teams to identify and resolve verification issues.
- Develop automation and scripting solutions using Python, Perl, and C/C++.
- Analyze regression failures, identify root causes, and improve overall test coverage and verification efficiency.
- Support subsystem and SOC integration, bring-up, and interoperability validation.


Required Skills & Experience


- 5–10+ years of experience in ASIC, SOC, or IP verification.
- Strong application/product engineering background with hands-on PCIe protocol verification experience.
- Deep knowledge of PCIe Gen1 through Gen6/Gen7 protocols and architectures.
- Strong understanding of PCIe link-up, LTSSM, enumeration, configuration space, device IDs, and interoperability.
- Experience validating PCIe IP at the IP, subsystem, and SOC levels.
- Hands-on experience with PCIe Root Complex and Endpoint configurations.
- Strong understanding of PCIe PHY/controller integration and interoperability.
- Experience with SystemVerilog RTL coding at IP and system-integration levels.
- Strong experience with UVM-based verification methodologies.
- Experience with one or more simulators such as Questa, VCS, or Xcelium.
- Experience developing and debugging C/C++ testbenches and firmware/software-driven verification flows.
- Strong scripting skills in Python, C, and/or Perl.
- Ability to understand and debug complex scripted simulation and regression environments.
- Experience modifying existing verification infrastructure and enhancing test suites.
- Strong debugging and problem-solving skills, particularly for complex PCIe bring-up and interoperability issues.


Preferred Qualifications


- Experience with AI/HPC and high-performance computing platforms.
- Experience with PCIe switches and complex multi-device system architectures.
- Experience with large-scale data center scale-up and scale-out architectures.
- Experience with multiple third-party PCIe IP and PHY implementations.
- Knowledge of firmware, BIOS, drivers, and software stacks involved in PCIe enumeration and device bring-up.
- Experience with pre-silicon validation and shift-left verification methodologies.
- Experience working with complex SOC integration environments.
- Strong understanding of PCIe compliance and interoperability testing.


Key Technical Areas

PCIe: Gen1, Gen2, Gen3, Gen4, Gen5, Gen6, Gen7

Verification: SystemVerilog, UVM, C/C++, Python, Perl

Simulation: Questa, VCS, Xcelium

Architecture: Root Complex, Endpoint, PCIe PHY, Controller, PCIe Switches

Debug: LTSSM, Link Training, Link Up, Enumeration, Device ID, Configuration Space, Interoperability

Environment: IP, Subsystem, SOC, Pre-Silicon, AI/HPC, Data Center

Ideal Candidate

The ideal candidate is a hands-on PCIe verification specialist who can independently debug complex
PCIe link-up, enumeration, interoperability, and SOC integration issues and can work across RTL, verification, firmware, software, PHY, and system-level environments.